• Full Time
  • Bangalore
  • Job ID: 2156
  • Salary (₹): Not Disclosed by Recruiter

Website USTGlobal US Technology International Pvt Ltd

US Technology International Pvt Ltd

We are a leading IT company with more than 14000 employees. We are one of the fastest companies to attain CMM Level 5, CMMi, and PCMM Level 5. We have vast experience in software solutions for areas like retail, banking & financial services, airlines, healthcare, shipping & transportation, networking, telecommunications automobiles and manufacturing.

Tagged as: atpg, bist, design for test, design for testability, DFT, issue resolution, quality improvement, scanning, silicon validation, simulation, test design

CTC: Not Disclosed
Job Position: DFT Engineer / Design for Test / Design for Testability
Required Experience: 2 - 7 yrs
Job Responsibility:
  1.  You are expertised in designing and Implementing DFT techniques (ATPG/Memory BIST/Scan /On-Chip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/Logic BIST) on complex SOCs to improve testability.
  2. You can perform Test coverage analysis, optimization, Pattern conversion (preferred), Pattern re-simulation and gate level simulation.
  3. You are able to interact with Cross functional teams for issue resolution.
  4. You can participate in driving new DFT methodology and solutions to improve quality, reliability and in-system
    testand debug capability.
Required Skills:

 

What you'll be doing:

1. You'll be responsible for implementing key cutting edge DFT logic modules,and verifying them.

2.These include test mode controllers,ATPG ,mbist, scan insertion and and post silicon validation.

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